1. Field of the Invention
The present invention relates to hysteresis in a digital circuit, and more specifically to a buffer with pseudo-ground hysteresis.
2. Art Background
In designing digital circuits and systems, noise immunity and stability, are important criteria. For example, an input digital signal to a digital switching circuit that contains noise may cause the digital switching circuit to transition to a different state due to the noise and not due to the informational content of the signal. To prevent multiple triggering of the digital circuit and to provide noise immunity, digital switching circuits often employ hysteresis. In general, a circuit utilizing electrical hysteresis generates an output based on both an input and on the recent history of the circuit. In a digital circuit employing hysteresis, once a first state transition occurs, the circuit requires a different signal trip point to cause a transition to a second state. The difference in the input signal required to generate the second state transition in the circuit is defined as the amount of hysteresis. A particular amount of hysteresis for a digital circuit is dependent upon the particular application. A typical design value for hysteresis is 150 mV, where the input transition point for switching from a first state to a second state is 150 mV less than for the input transition point for switching from the second state to first state.
A common application for employing hysteresis in digital circuits is TTL input stages utilizing CMOS input buffers. A first technique for employing hysteresis in a CMOS buffer is shown in FIG. 1a. The circuit contains a CMOS inverter having a p-channel MOSFET transistor 10, and a n-channel MOSFET transistor 30 as a first input stage. A p-channel MOSFET transistor 20 is coupled to the p-channel transistor 10. A second stage CMOS inverter 25 is implemented to enable the gate of the p-channel device--specifically the output of the second stage is fed back to the gate of device 20. In this configuration, hysteresis is provided when the second stage transitions thereby enabling the p-channel MOSFET 20 to change the voltage trip point of the first stage inverter. A second technique for implementing hysteresis in a CMOS buffer is use of a Schmitt trigger as shown in FIG. 1b. In addition to the CMOS buffer, comprising of n-channel and p-channel MOSFET transistors 40 and 50, and a current buffer 75, the Schmitt trigger configuration uses additional n-channel and p-channel MOSFET transistors 60 and 70 to lower the voltage trip point when the input transitions from a high logic level to a low logic level. However, neither technique provides noise immunity through electrical isolation from the ground plane. The present invention is a CMOS buffer utilizing a pseudo-ground hysteresis.